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ltc3613 1 3613fa typical application features description 24v, 15a monolithic step down regulator with differential output sensing the ltc ? 3613 is a monolithic synchronous step-down switching regulator capable of regulating outputs from 0.6v to 5.5v with up to 15a output current. the controlled on-time constant frequency valley current mode architecture allows for both fast transient response and constant frequency switch- ing in steady-state operation, independent of v in , v out and load. this also provides excellent current sharing capability. differential output voltage sensing along with a precision internal reference combine to offer 0.67% output regula- tion, even if the output ground reference deviates from local ground by 500mv. the switching frequency can be programmed from 200khz to 1mhz with an external resis- tor. the switching frequency is also phase synchronizable to an external clock in applications where switching noise/ emi reduction is crucial. very low t on and t off times allow for near 0% and near 100% duty cycles, respectively. voltage tracking soft start-up is provided for tracking and sequencing applications. safety fea- tures include output overvoltage protection, programmable current limit with foldback, and power good monitoring. high efficiency high power step-down converter efficiency and power loss vs load current applications n wide v in range: 4.5v to 24v; v out range: 0.6v to 5.5v at up to 15a n 0.67% output voltage accuracy n controlled on-time valley current mode architecture, excellent current sharing capability n frequency programmable from 200khz to 1mhz and synchronizable to external clock n r sense or inductor dcr current sensing with accurate current limit n fast transient response n differential output voltage sensing allowing 500mv common mode remote ground n t on(min) = 65ns; t off(min) = 105ns n overvoltage protection and current limit foldback n power good output voltage monitor n voltage tracking start-up n external v cc input for bypassing internal ldo n micropower shutdown: i q = 15a n 7mm 9mm 56-pin qfn package n distributed power system n point-of-load converters n servers v rng sv in pv in mode/pllin v out pgood run sense C sense + 100k 10 10 intv cc ltc3613 15k 10k 330f 2 0.47h 1.5m 0.1f 4.7f 82f v out 1.5v 15a 3613 ta01 v in 4.5v to 24v 0.1f 1000pf track/ss ith rt 115k 270pf 47pf 0.1f 21k extv cc sgnd boost sw intv cc pgnd v osns + v osns C + + l , lt, ltc, ltm, opti-loop, linear technology and the linear logo are registered trademarks and hot swap and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5487554, 6580258, 6304066, 6476589, 6774611. load current (a) 0.01 0 10 20 30 40 efficiency (%) 50 60 70 80 90 100 0.1 1 3613 ta01a 0 0.5 1.0 1.5 2.0 power loss (w) 2.5 3.0 3.5 10 v in = 12v v out = 1.5v pulse-skipping mode forced continuous mode
ltc3613 2 3613fa pin configuration absolute maximum ratings supply voltage (pv in , sv in ) ....................... C0.3v to 24v boost voltage ............................................ C0.3v to 30v sw voltage ................................................ C0.3v to 24v intv cc , extv cc , (boost-sw), mode /pllin, v rng , pgood, run voltages ....................... C0.3v to 6v v osns + , v osns C voltages ........ C0.6v to (intv cc + 0.3v) v out , sense +, sense C voltages ................. C0.6v to 6v rt, ith voltages ..................... C0.3v to (intv cc + 0.3v) track/ss voltages ..................................... C0.3v to 5v operating junction temperature range (notes 2, 4) ............................................ C40c to 125c storage temperature range .................. C65c to 150c (note 1) top view wkh package 56-lead (7mm 9mm) multipad qfn pv in 1 pv in 2 pv in 3 pv in 4 pv in 5 pv in 6 pv in 7 pv in 8 pv in 9 sw 10 boost 11 sgnd 12 pgood 13 sns + 14 sns C 15 sgnd 16 44 pgnd 43 pgnd 42 pgnd 41 pgnd 40 pgnd 39 pgnd 38 pgnd 37 pgnd 36 pgnd 35 sw 34 intv cc 33 intv cc 32 sv in 31 mode/pllin 30 extv cc 29 sgnd sgnd 17 v out 18 sgnd 19 v osns C 20 v oses + 21 track/ss 22 ith 23 v rng 24 rt 25 run 26 nc 27 sgnd 28 56 pv in 55 pv in 54 pv in 53 pv in 52 nc 51 sw 50 sw 49 sw 48 sw 47 sw 46 sw 45 sw pv in 57 sw 58 sgnd 59 t jmax = 125c, ja = 29c/w order information lead free finish tape and reel part marking* package description temperature range ltc3613ewkh#pbf ltc3613ewkh#trpbf ltc3613wkh 56-lead (7mm 9mm) plastic qfn C40c to 125c ltc3613iwkh#pbf ltc3613iwkh#trpbf ltc3613wkh 56-lead (7mm 9mm) plastic qfn C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc3613 3 3613fa symbol parameter conditions min typ max units main control loop v in input voltage operating range l 4.5 24 v v out output voltage operating range l 0.6 5.5 v i q input dc supply current normal shutdown supply current mode/pllin = intv cc run = 0v 2 15 4 25 ma a v reg regulated differential feedback voltage (v osns + C v osns C ) i th = 1.2v (note 3) t a = 25c t a = 0c to 85c t a = C40c to 125c l l 0.5985 0.596 0.594 0.6 0.6 0.6 0.6015 0.604 0.606 v v v regulated differential feedback voltage over line, load and common mode (v osns + C v osns C ) v in = 4.5v to 24v, ith = 0.5v to 1.9v, v osns C = 500mv (note 3) t a = 0c to 85c t a = C40c to 125c l l 0.594 0.591 0.6 0.6 0.606 0.609 v v t on(min) minimum on-time 65 ns t off(min) minimum off-time 105 ns g m(ea) error amplifier transconductance i th = 1.2v (note 3) l 1.4 1.7 2 ms v sense(max) valley current sense threshold, v sense + C v sense C , peak current = valley + ripple v rng = 2v, v fb = 0.57v v rng = 0v, v fb = 0.57v v rng = intv cc , v fb = 0.57v l l l 80 22 39 100 30 50 120 38 61 mv mv mv v sense(min) minimum current sense threshold,v sense + C v sense C , force continuous operation v rng = 2v, v fb = 0.63v v rng = 0v, v fb = 0.63v v rng = intv cc , v fb = 0.63v C50 C15 C25 mv mv mv v sense(cm) sense + , sense C voltage range (common mode) l C0.5 5.5 v i sense sense + , sense C input bias current v sense(cm) = 0.6v v sense(cm) = 5v 5 1 50 4 na a v run(th) run pin on threshold v run rising l 1.1 1.2 1.3 v v run(hys) run pin hysteresis 80 mv i ss soft-start charging current v trackss = 0v 1.0 a uvlo intv cc undervoltage lockout intv cc undervoltage lockout release falling rising l l 3.4 3.65 4.2 4.0 4.5 v v i vosns + v osns + input bias current v fb = 0.6v 5 25 na i vosns C v osns C input bias current v fb = 0.6v C15 C50 a the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. sv in = 15v, v fb = v osns + C v osns C , unless otherwise noted. (note 4) electrical characteristics
ltc3613 4 3613fa the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. sv in = 15v, v fb = v osns + C v osns C , unless otherwise noted. (note 4) note 1: stresses beyond those listed under absolute maximum ratings cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: t j is calculated from the ambient temperature, t a , and power dissipation, p d , as follows: t j = t a + (p d ? 29c/w) ( ja is simulated per jesd51-7 high effective thermal conductivity test board) jc =1c/w ( jc is simulated when heat sink is applied at the bottom of the package.) note 3: the ltc3613 is tested in a feedback loop that adjusts v fb = v osns + C v osns C to achieve a specified error amplifier output voltage (ith). note 4: the ltc3613 is tested under pulsed load conditions such that t j t a . the ltc3613e is guaranteed to meet specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3613i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 5: delay times are measured using 50% levels. symbol parameter conditions min typ max units oscillator and clock synchronization f osc free running switching frequency r t = 205k r t = 80.6k r t = 38.8k 175 450 900 200 500 1000 225 550 1100 khz khz khz clk ih clock input high level into mode/pllin 2 v clk il clock input low level into mode/pllin 0.5 v internal v cc regulator and external v cc intv cc internal v cc voltage 6v < v in < 24v 5.1 5.3 5.55 v intv cc(%) internal v cc load regulation i cc = 0ma to 50ma C1 C2 % extv cc(th) extv cc switchover voltage extv cc rising 4.4 4.6 4.75 v extv cc(hys) extv cc switchover hysteresis 200 mv intv cc extv cc voltage drop v extvcc = 5v. i cc = 50ma 200 mv pgood output pgd ov pgood upper threshold v fb rising (with respect to regulated feedback voltage v reg ) 5 7.5 10 % pgd uv pgood lower threshold v fb falling (with respect to regulated feedback voltage v reg ) C10 C7.5 C5 % pgd hys pgood hysteresis v fb returning 2 % v pgd(lo) pgood low voltage i pgood = 5ma 0.15 0.4 v t pgd(fall) delay from ov/uv fault to pgood falling (note 5) 20 s t pgd(rise) delay from ov/uv recovery to pgood rising (note 5) 10 s r ds(on) r ds(on) top switch on-resistance bottom switch on-resistance 7.5 5.5 mohm mohm electrical characteristics
ltc3613 5 3613fa typical performance characteristics transient response: pulse-skipping mode load step: pulse-skipping mode load release: pulse-skipping mode normal soft start-up soft start-up into a pre-biased output output tracking transient response: forced continuous mode load step: forced continuous mode load release: forced continuous mode i load 10a/div v out 100mv/div 40s/div 3613 g01 load transient = 0a to 15a v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div i load 10a/div v out 100mv/div 10s/div 3613 g02 load step = 0a to 15a v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div i load 10a/div v out 100mv/div 10s/div 3613 g03 load release = 15a to 0a v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div i load 10a/div v out 100mv/div 40s/div 3613 g04 load transient = 500ma to 15a v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div i load 10a/div v out 100mv/div 10s/div 3613 g05 load step = 500ma to 15a v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div i load 10a/div v out 100mv/div 10s/div 3613 g06 load release = 15a to 500ma v in = 12v, v out = 1.5v figure 10 circuit i l 10a/div v in 5v/div track/ss 500mv/div 4ms/div 3613 g07 v in = 12v v out = 1.5v figure 10 circuit v out 1v/div track/ss 500mv/div 2ms/div 3613 g08 v in = 12v v out = 1.5v figure 10 circuit v out 1v/div v in 5v/div v out pre-biased to 0.75v track/ss 500mv/div 10ms/div 3613 g09 v in = 12v v out = 1.5v figure 10 circuit v out 1v/div t a = 25c unless otherwise noted
ltc3613 6 3613fa typical performance characteristics output regulation vs input voltage output regulation vs load current output regulation vs temperature switching frequency vs input voltage switching frequency vs load current non-synchronized switching frequency vs temperature overcurrent protection short-circuit protection overvoltage protection 4ms/div 7.5a 3613 g10 v in = 12v v out = 1.5v figure 10 circuit v out 1v/div load-step trigger i load 10a/div v out droops due to reaching current limit note 200s/div 3613 g11 v in = 12v v out = 1.5v figure 10 circuit v out 1v/div i load 10a/div short- circuit trigger note: inductor current reaches current limit before foldback and during short-circuit recovery short-circuit region 20s/div 3613 g12 v in = 12v v out = 1.5v figure 10 circuit note: sw is forced low for extended periods to remove overvoltage v out 200mv/div i l 10a/div sw 20v/div overvoltage trigger overvoltage region input voltage (v) 0 C0.5 v out error (%) C0.3 C0.1 0.1 0.3 0.5 48 3613 g13 12 16 20 24 v in = 12v i load = 5a figure 10 circuit load current (a) 0 v out error (%) 0.3 0.1 12 3613 g14 C0.1 C0.3 C0.5 3 6 9 15 0.5 v in = 12v i load = 4a figure 10 circuit temperature (c) C50 C0.2 normalized v out (%) C0.1 0 0.1 0.2 C25 0 25 50 3613 g15 55 100 125 150 v in = 12v i load = 0a v out normalized at t a = 25c figure 10 circuit v in (v) 0 C1.0 normalized f (%) C0.5 0 0.5 1.0 8 16 24 3613 g16 1.5 2.0 4 12 20 v in = 12v i load = 5a figure 10 circuit load current (a) 0 normalized f (%) C0.1 0.1 0.3 12 3613 g17 C0.3 C0.5 3 6 9 15 0.5 v in = 12v i load = 4a figure 10 circuit temperature (c) C50 C2.0 normalized f (%) C1.5 C1.0 C0.5 0 050 100 150 3613 g18 0.5 1.0 C25 25 75 125 v in = 12v i load = 0a frequency normalized at t a = 25c figure 10 circuit t a = 25c unless otherwise noted
ltc3613 7 3613fa typical performance characteristics error amplifier transconductance vs temperature current sense voltage vs ith voltage maximum current sense voltage vs temperature run thresholds vs temperature input undervoltage lockout thresholds vs temperature run and track/ss pull-up currents vs temperature temperature (c) C50 1.50 transconductance (ms) 1.55 1.60 1.65 1.70 050 100 150 3613 g22 1.75 1.80 C25 25 75 125 ith voltage (v) 0 C60 current sense voltage (mv) C40 0 20 40 1 2 2.5 120 3613 g23 C20 0.5 1.5 60 80 100 v rng = 0.6v v rng = 0.9v v rng = 1.3v v rng = 1.6v v rng = 2.0v temperature (c) C5 0 0 maximum current sense voltage (mv) 20 40 60 80 050 100 150 3613 g24 100 120 C25 25 75 125 v rng = 2v v rng = 1v v rng = 0.6v temperature (c) C50 run pin thresholds (v) 0.8 1.2 150 3613 g25 0.4 0 0 50 100 C25 25 75 125 1.6 0.6 1.0 0.2 1.4 switching region standby region shutdown region temperature (c) C50 3.3 uvlo thresholds (v) 3.5 3.7 3.9 4.1 050 100 150 3613 g26 4.3 4.5 C25 25 75 125 uvlo release (intv cc rising) uvlo lock (intv cc falling) temperature (c) C50 0.6 current (a) 0.8 1.0 1.2 1.4 050 100 150 3613 g27 1.6 1.8 run C25 25 75 125 track/ss t a = 25c unless otherwise noted
ltc3613 8 3613fa pin functions pv in (pins 1-9, 53-56, 57 exposed pad): power supply inputs. these pins connect to the drain of the internal power mosfets. the pv in exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. the supply voltage can range from 4.5v to 24v. the voltage on this pin is also used to adjust the tg on-time in order to maintain constant frequency operation. sw (pins 10, 35, 45-51, 58 exposed pad): switch node connection. the (C) terminal of the bootstrap capacitor, c b , connects to this node. this pin swings from a diode voltage below ground up to v in . the sw exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. boost (pin 11): boosted driver supply connection. the (+) terminal of the bootstrap capacitor, c b , as well as the cathode of the schottky diode, d b , connects to this node. this node swings from intv cc C v schottky to v in + intv cc C v schottky . sgnd (pins 12, 16, 17, 19, 28, 29, 59 exposed pad): signal ground connection. the sgnd exposed pad must be soldered to the circuit board for electrical contact and rated thermal performance. all small-signal components should be connected to the signal ground. connect signal ground to power ground only at one point using a single pcb trace. pgood (pin 13): power good indicator output. this open-drain logic output is pulled to ground when the output voltage is outside of a 7.5% window around the regulation point. sense + (pin 14): differential current sensing (+) input. for r sense current sensing, kelvin (4-wire) connect sense + and sense C pins across the sense resistor. for dcr sensing, kelvin connect sense + and sense C pins across the sense filter capacitor. sense C (pin 15): differential current sensing (C) input. for r sense current sensing, kelvin (4-wire) connect the sense + and sense C pins across the sense resistor. for dcr sensing, kelvin connect the sense + and sense C pins across the sense filter capacitor. v out (pin 18): output voltage sense for adjusting the on-time for constant frequency operation. tying this pin to the local output (instead of the remote output) is recom- mended for most applications. this pin can be programmed as needed for achieving the steady-state on-time required for constant frequency operation. v osns C (pin 20): differential output sensing (C) input. connect this pin to the negative terminal of the output capacitor. there is a bias current of 35a (typical) flowing out of this pin. v osns + (pin 21): differential output sensing (+) input. connect this pin to the feedback resistor divider between the positive and negative output capacitor terminals. in normal operation the ltc3613 will regulate the differen- tial output voltage which is divided down to 0.6v by the feedback resistor divider. track/ss (pin 22): external tracking and soft-start input. the ltc3613 regulates the differential feedback voltage (v osns + ? v osns C ) to the smaller of 0.6v or the voltage on the track/ss pin. an internal 1.0a pull-up current source is connected to this pin. a capacitor to ground at this pin sets the ramp time to the final regulated output voltage. alternatively, another voltage supply connected through a resistor divider to this pin allows the output to track the other supply during start-up. ith (pin 23): current control voltage and switching regu- lator compensation point. the current sense threshold increases with this control voltage which ranges from 0v to 2.4v. v rng (pin 24): current sense voltage range input. the maximum allowed sense voltage between sense + and sense C is equal to 0.05 ? v rng . if v rng is tied to sgnd, the device operates with a maximum sense voltage of 30mv. if v rng is tied to intv cc , the device operates with a maximum sense voltage of 50mv. rt (pin 25): switching frequency programming pin. connect an external resistor from rt to signal ground to program the switching frequency between 200khz and 1mhz. an external clock applied to mode/pllin must be within 30% of this free-running frequency to ensure frequency lock.
ltc3613 9 3613fa pin functions run (pin 26): digital run control input. run self biases high with an internal 1.3a pull-up. forcing run below 1.2v disables switching. taking run below 0.75v shuts down all bias and places the ltc3613 into micropower shutdown mode of approximately 15a. extv cc (pin 30): external v cc input. when extv cc exceeds 4.6v, an internal switch connects this pin to intv cc and shuts down the internal regulator so that the controller and gate drive power is drawn from extv cc . extv cc should not exceed v in . mode/pllin (pin 31): external clock synchronization input and/or forced continuous mode input. when an external clock is applied to this pin, the rising switching cycle will be synchronized with the rising edge of the external clock. additionally, this pin determines operation under light load conditions. when either a clock input is detected or mode/pllin is tied to intv cc , forced continu- ous mode operation is selected. tying this pin to sgnd allows discontinuous pulse-skipping mode operation at light loads. sv in (pin 32): signal input supply. this pin powers the internal control circuitry. intv cc (pins 33, 34): internal 5.3v regulator output. the driver and control circuits are powered from this voltage. decouple this pin to power ground with a minimum of 4.7f ceramic capacitor (c vcc ). the anode of the schottky diode, d b , connects to this pin. pgnd (pins 36-44): power ground connection. connect this pin as close as practical to the (C) terminal of c vcc and the (C) terminal of c in .
ltc3613 10 3613fa functional diagram C + C + i cmp ea (g m(ea) = 1.7ms) 0.645v 0.555v 0.6v 1a i rev logic control pll system one-shot timer clock detect oscillator ldo out en in sv in 4.2v time adjust stop start 1.2v 0.75v C + + C + da (a = 1) r pgd pgood mode/pllin v rng ith v osns C v osns + track/ss sense C sense + pgnd sw extv cc bo0st input supply d b c b mt mb l c out r fb2 r fb1 r sense pv in intv cc intv cc sgnd r ith c ith1 intv cc r1 intv cc r2 3.65v uvlo 4.6v v out rt rt run 1.3a c vcc v in c in v out c in c ss 3613 fd + C uv + C + C C + C C ov + C tg drv bg drv clock operation main control loop the ltc3613 uses valley current mode control to regulate the output voltage in a monolithic, all n-channel mosfet dc/dc step-down converter. current control is achieved by sensing the inductor current across sense + and sense C , either by using an explicit resistor connected in series with the inductor or by implicitly sensing the inductors resis- tive (dcr) voltage drop through an rc filter connected across the inductor. in normal steady-state operation, the top mosfet is turned on for a fixed time interval proportional to the delay in the one-shot timer. the pll system adjusts the delay in the one-shot timer until the top mosfet turn-on is synchro- nized either to the internal oscillator or the external clock input if provided. as the top mosfet turns off, the bottom mosfet turns on with a small time delay (dead time) to avoid shoot-through current. the next switching cycle is initiated when the current comparator, i cmp , senses that inductor current has reached the valley threshold point (refer to functional diagram)
ltc3613 11 3613fa operation (refer to functional diagram) and turns the bottom mosfet off immediately and the top mosfet on. again in order to avoid shoot-through current there is a small dead time delay before the top mosfet turns on. the voltage on the ith pin sets the i cmp valley threshold point. the error amplifier, ea, adjusts this ith voltage by comparing the differential feedback signal, v osns + ? v osns C , to a 0.6v internal reference voltage. consequently, the ltc3613 regulates the output voltage by forcing the differential feedback voltage to be equal to the 0.6v internal reference. the difference amplifier, da, converts the dif- ferential feedback signal to a single-ended input for the ea. if the load current increases, it causes a drop in the differential feedback voltage relative to the reference. the ea forces ith voltage to rise until the average inductor current again matches the load current. differential output sensing the output voltage is resistively divided externally to create a feedback voltage for the controller. the internal difference amplifier, da, senses this feedback voltage along with the outputs remote ground reference to create a differential feedback voltage. this scheme overcomes any ground offsets between local ground and remote output ground, resulting in a more accurate output voltage. the ltc3613 allows for remote output ground deviations as much as 500mv with respect to local ground. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. power on the intv cc pin is derived in two ways: if the extv cc pin is below 4.6v, then an internal 5.3v low dropout linear regulator, ldo, supplies intv cc power from pv in ; if the extv cc pin is tied to an external source larger than 4.6v, then the ldo is shut down and an internal switch shorts the extv cc pin to the intv cc pin, thereby powering the intv cc pin with the external source and helping to increase overall efficiency and decrease internal self heating through power dissipated in the ldo. this external power source could be the output of the step-down switching regulator itself if the output is programmed to higher than 4.6v. the top mosfet driver is biased from the floating boot- strap capacitor, c b , which normally recharges during each off cycle through an external schottky diode when the top mosfet turns off. if the v in voltage is low and intv cc drops below 3.65v, undervoltage lockout circuitry disables the external mosfet driver and prevents the power switches from turning on. shutdown and start-up the ltc3613 can be shut down using the run pin. pull- ing this pin below 1.2v prevents switching, and less than 0.75v disables most of the internal bias circuitry, including the intv cc regulator. when run is less than 0.75v, the shutdown i q is about 15a. pulling the run pin between 0.75v and 1.2v enables the controller into a standby mode where all internal circuitry is powered-up except for the mosfet driver. the standby i q is about 2ma. releasing the run pin from ground allows an internal 1.3a current to pull the pin above 1.2v and fully enable the controller including the mosfet driver. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. when pulled up by a resistor to an external voltage, the run pin will sink about 35a of current before reaching 6v. if the external voltage is above 6v (e.g., v in ), select a large enough resistor value so that the voltage on run will not exceed 6v. the start-up of the output voltage, v out , is controlled by the voltage on the track/ss pin. when the voltage on the track/ss pin is less than the 0.6v internal reference, the ltc3613 regulates the differential feedback voltage to the track/ss voltage instead of the 0.6v reference. this allows the track/ss pin to be used for programming a ramp-up time for v out by connecting an external capacitor from the track/ss pin to sgnd. an internal 1a pull-up current charges this capacitor, creating a voltage ramp on the track/ss pin. as the track/ss voltage rises from 0v to 0.6v (and beyond), the ltc3613 forces the output voltage, v out , to ramp up smoothly to its final value. alternatively, the track/ss pin can be used to track the start-up of v out to another external supply as in a master slave configuration. typically, this requires connecting a resistor divider from the master supply to the track/ss pin (see soft-start and tracking).
ltc3613 12 3613fa operation when the run pin is pulled low to disable the controller or when intv cc drops below its undervoltage lockout thresh- old of 3.65v, the track/ss pin is pulled low internally. light load current operation when the dc load current is less than 1/2 of the peak- to-peak inductor current ripple, the inductor current can drop to zero or become negative. if the mode/pllin pin is connected to sgnd, the ltc3613 will transition into discontinuous mode operation (also called pulse-skipping mode), where a current reversal comparator, i rev , detects and prevents negative inductor current by shutting off the bottom mosfet, mb. in this mode, both switches remain off with the output capacitor supplying the load current. as the output capacitor discharges and the output volt- age droops lower, the ea will eventually move the ith voltage above the zero current level to initiate another switching cycle. if the mode/pllin pin is tied to intv cc or an external clock is applied to mode/pllin, the ltc3613 will be forced to operate in continuous mode (forced continuous mode) and not transition into discontinuous mode. in this case the current reversal comparator, i rev , is disabled, allowing the inductor current to become negative and thus maintain constant frequency operation. frequency selection and external clock synchronization the steady-state switching frequency of the ltc3613 is set by an internal oscillator. the frequency of this internal oscillator can be programmed from 200khz to 1mhz by connecting a resistor from the rt pin to sgnd. the rt pin is forced to 1.2v internally. a phase-locked loop (pll) system synchronizes the turn-on of the switching cycle to this internal oscillator when no external clock is provided. for applications with stringent frequency or interfer- ence requirements, an external clock source connected to the mode/pllin pin can be used to synchronize the switching cycle turn-on to the rising edge of the clock. the ltc3613 operates in forced continuous mode when it is synchronized to the external clock. the external clock frequency has to be within 30% of the internal oscillator frequency for successful synchronization and the clock input levels should be greater than 2v for hi and less than 0.5v for lo. the mode/pllin pin has an internal 600k pull-down resistor. power good and fault protection the power good pin, pgood, is connected internally to an open-drain n-channel mosfet. an external pull-up resistor to a voltage supply of up to 6v (or intv cc ) completes the power good detection scheme. overvoltage and undervolt- age comparators ov and uv turn on the mosfet and pull the pgood pin low when the differential feedback voltage is outside a 7.5% window of the 0.6v reference voltage. the pgood pin is also pulled low when the ltc3613 is in the soft-start or tracking phase, when in undervoltage lockout, or when the run pin is low (shut down). when the differential feedback voltage is within the 7.5% requirement, the open-drain nmos is turned off and the pin is pulled up by an external resistor. there is an internal delay of 10s before the pgood pin will indicate power good once the differential feedback voltage is within the 7.5% window. when the feedback voltage goes out of the 7.5% window, there is an internal 20s delay before pgood is pulled low. in an overvoltage condition, mt is turned off and mb is turned on immediately without any delay and held on until the overvoltage condition clears. foldback current limiting is provided if the output is shorted to ground. as the differential feedback voltage drops, the current threshold voltage on the ith pin is pulled down and clamped to 1.2v. this reduces the inductor valley current level to one-fourth of its maximum value as the differential feedback approaches 0v. foldback current limiting is disabled at start-up.
ltc3613 13 3613fa the typical application on the first page of this data sheet is a basic ltc3613 application circuit. the ltc3613 can be configured to sense the inductor current either through a series sense resistor, r sense , or through an rc filter across the inductor (dcr). the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, cur- rent sensing resistors provide the most accurate current limits for the controller. once the required output voltage and operating frequency have been determined, external component selection is driven by load requirements, and begins with the selection of inductor and current sensing components. next, the proper current sense threshold is programmed using the v rng pin. finally, input and output capacitors are selected. output voltage programming and differential output sensing the ltc3613 integrates differential output sensing with output voltage programming, allowing for simple and seamless design. as shown in figure 1, the output voltage is programmed by an external resistor divider from the regulated output point to its ground reference. the resis- tive divider is tapped by the v osns + pin, and the ground reference is sensed by v osns C . an optional feed-forward capacitor, c ff , can be used to improve the transient per- formance of the regulator system as discussed under opti-loop ? compensation. the resulting output voltage is given according to the following equation: applications information v out =0.6v? 1+ r fb2 r fb1 ? ? ? ? ? ? more precisely, the v out value programmed in the previous equation is with respect to the outputs ground reference, and thus is a differential quantity. for example, if v out is programmed to 5v and the output ground reference is at C0.5v, then the output will be 4.5v with respect to signal ground. the minimum differential output voltage is limited to the internal reference, 0.6v, and the maximum differential output voltage is 5.5v. figure 1. setting output voltage r fb2 v osns + sw ltc3613 v osns C c out c ff (opt) 3613 f01 v out r fb1 the v osns + pin is high impedance with no input bias cur- rent. the v osns C pin has about 35a of current flowing out of the pin. differential output sensing allows for more accurate output regulation in high power distributed systems having large line losses. figure 2 illustrates the potential variations in the power and ground lines due to parasitic elements. these variations are exacerbated in multi-application systems with shared ground planes. without differential output sensing, these variations directly reflect as an error in the regulated output voltage. the ltc3613s differential output sensing can correct for up to 500mv of variation in the outputs power and ground lines. the ltc3613s differential output sensing scheme is distinct from conventional schemes where the regulated output and its ground reference are directly sensed with a difference amplifier whose output is then divided down with an external resistive divider and fed into the error amplifier input. this conventional scheme is limited by the common mode input range of the difference amplifier and typically limits differential sensing to the lower range of output voltages. the ltc3613 allows for seamless differential output sensing by sensing the resistively divided feedback volt- age differentially. this allows for differential sensing in the full output range from 0.6v to 5.5v. the difference amplifier of the ltc3613 has a C3db bandwidth of 8mhz, high enough to not affect main loop compensation and transient behavior.
ltc3613 14 3613fa applications information to avoid noise coupling into v osns + , the resistor divider should be placed near the v osns + and v osns C pins and physically close to the ltc3613. the remote output and ground traces should be routed together as a differential pair to the remote output. these traces should be termi- nated as close as physically possible to the remote output point that is to be accurately regulated through remote differential sensing. switching frequency programming the choice of operating frequency is a trade-off between efficiency and component size. lowering the operating fre- quency improves efficiency by reducing mosfet switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. conversely, raising the operating frequency degrades efficiency but reduces component size. the switching frequency of the ltc3613 can be pro- grammed from 200khz to 1mhz by connecting a resistor from the rt pin to signal ground. the value of this resistor is given by the following empirical formula: r t k [] = 41550 fkhz [] C2.2 r fb1 sw r fb2 l c in v in c out1 c out2 3613 f02 i load other currents flowing in shared ground plane power trace parasitics v drop(pwr) + C ground trace parasitics v drop(gnd) i load ltc3613 v osns + pgnd pv in v osns C figure 2. differential output sensing used to correct line loss variations in a high power distributed system with a shared ground plane not counting resistor tolerances, the switching fre- quency could still have a 10% deviation from the ideal programmed value. the internal pll has a synchroniza- tion range of 30% around this programmed frequency. therefore, during external clock synchronization be sure that the external clock frequency is within this 30% range of the rt programmed frequency. it is advisable that the rt programmed frequency be equal to the external clock for maximum synchronization margin. refer to phase and frequency synchronization for further details. inductor selection the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower efficiency because of mosfet gate charge losses and top mosfet transition losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered.
ltc3613 15 3613fa applications information the inductor value has a direct effect on ripple current. the inductor ripple current, i l , decreases with higher inductance or frequency and increases with higher v in : i l = v out f?l ?1C v out v in ? ? ? ? ? ? accepting larger values of i l allows the use of low induc- tances, but results in higher output voltage ripple, higher esr losses in the output capacitor, and greater core losses. a reasonable starting point for setting ripple current is i l = 0.4 ? i out(max) where i out(max) is the maximum output current for the application. the maximum i l occurs at the maximum input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductance should be chosen according to: l= v out f ? i l(max) ? 1C v out v in(max) ? ? ? ? ? ? once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot tolerate the core loss of low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy or kool m cores. ferrite core material saturates hard, meaning that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! a variety of inductors designed for high current, low volt- age applications are available from manufacturers such as sumida, panasonic, coiltronics, coilcraft, toko, vishay, pulse and wrth. current sense pins and current limit programming inductor current is sensed through the sense + and sense C pins and fed into the internal current compara- tors. the common mode input voltage range of the cur- rent comparators is C0.5v to 5.5v. both sense pins are high impedance inputs. when the common mode range is between C0.5v to 1.1v, there is no input bias current, and when between 1.4v and 5.5v, there is less than 1a of current flowing into the pins. between 1.1v and 1.4v, the input bias current will be zero if the common mode voltage is ramped up from 1.1v and less than 1a if the common mode voltage is ramped down from 1.4v. the high impedance inputs to the current comparator allow accurate dcr sensing. however, care must be taken not to float these pins during normal operation. the maximum allowed sense voltage v sense(max) between sense + and sense C is set by the voltage applied to the v rng pin and is given by: v sense(max) = 0.05 ? v rng the current mode control loop does not allow the induc- tor current valleys to exceed 0.05 ? v rng . the maximum output current is given by: i out(max) = v sense(max) r sense + 1 2 i l the v sense(max) is shown in the figure maximum current sense voltage vs temperature in the typical performance characteristics. note that ith is close to 2.4v when in current limit. an external resistive divider from intv cc can be used to set the voltage on the v rng pin between 0.6v and 2v, resulting in maximum sense voltages between 30mv and 100mv. the wide voltage sense range allows for a variety of applications. the v rng pin can also be tied to either sgnd or intv cc to force internal defaults. when v rng is tied to sgnd, the device operates with a maximum sense voltage of 30mv. when the v rng pin is tied to intv cc , the device operates with a maximum sense voltage of 50mv. when setting current limit, ensure that the junction temperature does not exceed the rating of 125c.
ltc3613 16 3613fa applications information r sense inductor current sensing a typical r sense inductor current sensing scheme is shown in figure 3. r sense is chosen based on the required maximum output current. given the maximum current, i out(max) , maximum sense voltage, v sense(max) , set by the v rng pin, and maximum inductor ripple current, i l(max) , the value of r sense can be chosen as: r sense = v sense(max) i out(max) C i l(max) 2 conversely, given r sense and i out(max) , v sense(max) and thus the v rng voltage could be determined from the above equation. to assure that the maximum rated output current can be supplied for different operating conditions and component variations, sufficient design margin should be built into these calculations. because of possible pcb noise in the current sensing loop, the current ripple of v sense = i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 10mv v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. for todays highest current density solutions the value of the sense resistor can be less than 1m and the maxi- mum sense voltage can be as low as 30mv. in addition, inductor ripple currents greater than 50% with operation up to 1mhz are becoming more common. under these conditions, the voltage drop across the sense resistors parasitic inductance becomes more relevant. a small rc filter placed near the ic has been traditionally used to re- duce the effects of capacitive and inductive noise coupled in the sense traces on the pcb. a typical filter consists of two series 10 resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. the filter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin (4-wire) connected to the sense resistor. dcr inductor current sensing for applications requiring higher efficiency at high load currents, the ltc3613 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 4. the dcr of the inductor represents the small amount of dc winding resistance, which can be less than 1m for to- days low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resistor would cost several points of efficiency compared to dcr sensing. r f r esl r sense resistor and parasitic inductance filter components placed near sense pins r f sense + sw ltc3613 sense C c f 3613 f03 v out figure 3. r sense current sensing r1 r2 (opt) dcrl inductor l/dcr = (r1||r2) c1 c1 near sense pins sense + sw ltc3613 sense C c1 3613 f04 v out c out figure 4. dcr current sensing
ltc3613 17 3613fa applications information the inductor dcr is sensed by connecting an rc filter across the inductor. this filter typically consists of one or two resistors (r1 and r2) and one capacitor (c1) as shown in figure 4. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr multiplied by r2/(r1 + r2). therefore, r2 may be used to scale the voltage across the sense terminals when the dcr is greater than the target sense resistance. with the ability to program current limit through the v rng pin, r2 may be optional. c1 is usually selected to be in the range of 0.01f to 0.47f. this forces r1|| r2 to around 2k to 4k, reducing error that might have been caused by the sense pins input bias currents. the first step in designing dcr current sensing is to determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 25c. increase this value to account for the temperature coef- ficient of resistance, which is approximately 0.4%/c. a conservative value for inductor temperature t l is 100c. the dcr of the inductor can also be measured using a good rlc meter, but the dcr tolerance is not always the same and varies with temperature; consult the manufacturers datasheets for detailed information. from the dcr value, v sense(max) is calculated as: v sense(max) =dcr max at 25c ? 1+0.4% t l(max) C25c () ? ? ? ? ? i out(max) C i l /2 ? ? ? ? if v sense(max) is within the maximum sense voltage of the ltc3613 as programmed by the v rng pin (30mv to 100mv), then the rc filter only needs r1. if v sense(max) is higher, then r2 may be used to scale down the maximum sense voltage so that it falls within range. the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p loss r1 () = v in(max) Cv out () ? v out r1 ensure that r1 has a power rating higher than this value. if high efficiency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or r sense sensing. light load power loss can be modestly higher with a dcr network than with a sense resistor due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc- tion losses and provides higher efficiency at heavy loads. peak efficiency is about the same with either method. to maintain a good signal-to-noise ratio for the current sense signal, use a minimum v sense of 10mv. for a dcr sensing application, the actual ripple voltage will be determined by: v sense = v in Cv out r1 ? c1 ? v out v in ? f operating multiple units in parallel the ltc3613s current mode control architecture makes it straightforward to parallel multiple units for higher output current. figure 13 shows an example circuit of two ltc3613s placed in parallel to provide 30a at 1.2v from a 6v to 24v input. the signals at mode/pllin are 180 out of phase, to reduce stress on the input and output capacitors. since the ith pin voltage determines the cycle-by-cycle valley inductor current, sharing is achieved by connecting the ith pins together. because the ith pin is sensitive to noise, a small 22pf to 47pf decoupling capacitor should
ltc3613 18 3613fa applications information be placed close to each ith pin. if a compensation scheme is stable on a single phase application, a polyphase ap- plication with n phases should be compensated as: c ith1 = n ? c ith(single) , c ith2 = n ? c ith2(single) and r ith = r ith(single) /n. the track/ss pins should be connected together so that all ltc3613s start up with the same slew rate. the v osense + pins of paralleled ltc3613s should be connected together to prevent any false triggering of overvoltage and short circuit protection. only one divider is necessary. the remote output and ground traces should be routed together as differential pairs and terminated at the same remote sensing location (preferably kelvin connected across the bulk capacitors at the remote output point). the smaller value ceramic input and output capacitors, however, should be in close proximity to the ics. c in and c out selection in continuous mode, the current into pv in is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor cur- rent is given by: i rms ? i out(max) ? v out v in ? v in v out C1 this formula has a maximum at v in = 2v out , where i rms = i out(max) /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufactur- ers ripple current ratings for electrolytic and conductive polymer capacitors are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. the selection of c out is primarily determined by the effec- tive series resistance, esr, to minimize voltage ripple. the output ripple, v out , in continuous mode is determined by: v out i l r esr + 1 8 ? f ? c out ? ? ? ? ? ? the output ripple is highest at maximum input voltage since i l increases with input voltage. typically, once the esr requirement for c out has been met, the rms current rating generally far exceeds the peak-to-peak current ripple requirement. the choice of using smaller output capaci- tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount pack- ages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezo- electric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. when using ceramic input capacitors, care must be taken to ensure that ringing from inrush currents and switching does not pose an overvoltage hazard to the regulator. for high switching frequencies, reducing output ripple and better emi filtering may require small-value capacitors that have low esl (and correspondingly higher self resonant frequencies) to be placed in parallel with larger value capacitors that have higher esl. this will ensure good noise and emi filtering in the entire frequency spectrum of interest. even though ceramic capacitors generally have good high frequency performance, small ceramic capacitors may still have to be parallel connected with large ones to optimize performance.
ltc3613 19 3613fa top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. this capacitor is charged through diode d b from intv cc when the switch node is low. when the top mosfet turns on, the switch node rises to v in and the boost pin rises to approximately pv in + intv cc . the boost capacitor needs to store approximately 100 times the gate charge required by the top mosfet. in most applications a 0.1f to 0.47f, x5r or x7r dielectric capacitor is adequate. it is recommended that the boost capacitor be no larger than 10% of the intv cc capacitor, c vcc , to ensure that the c vcc can supply the upper mosfet gate charge and boost capacitor under all operating conditions. variable frequency in response to load steps offers superior transient performance but requires higher instantaneous gate drive. gate charge demands are greatest in high frequency low duty factor applications under high di/dt load steps and at start-up. in order to minimize sw node ringing and emi, connect a 5 to 10 resistor in series with the boost pin. make the c b and d b connections on the other side of the resistor. this series resistor helps to slow down the sw node rise time, limiting the high di/dt current through the top mosfet that causes sw node ringing. intv cc regulator and extv cc power the ltc3613 features a pmos low dropout linear regulator (ldo) that supplies power to intv cc from the sv in supply. intv cc powers much of the ltc3613s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5.3v. the ldo can supply a maximum current of 50ma rms and must be bypassed to ground with a minimum of 4.7f ceramic capacitor. good bypassing is needed to supply the high transient currents required by the power mosfet gate drivers. applications information when the voltage applied to extv cc pin rises above 4.6v, the intv cc ldo is turned off and the extv cc is connected to intv cc with an internal switch. this switch remains on as long as the voltage applied to extv cc remains above 4.4v. using the extv cc allows the mosfet driver and control power to be derived from the ltc3613s switching regulator output during normal operation and from the ldo when the output is out of regulation (e.g., start-up, short circuit). if more than 50ma rms current is required through extv cc , then an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that this external voltage source is less than sv in . significant efficiency and thermal gains can be realized by powering intv cc from the switching regulator output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5.3v ldo resulting in an efficiency penalty of up to 10% at high input voltages. 2. extv cc connected directly to switching regulator output v out > 4.6v. this provides the highest efficiency. 3. extv cc connected to an external supply. if a 4.6v or greater external supply is available, it may be used to power extv cc provided that the external supply is suf- ficient enough for mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3v and other low voltage converters, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.6v.
ltc3613 20 3613fa applications information for applications where the main input power is less than 5.3v, tie the v in and intv cc pins together and tie the combined pins to the pv in input with an optional 1 or 2.2 resistor as shown in figure 5 to minimize the voltage drop caused by the gate charge current. this will override the intv cc ldo and will prevent intv cc from dropping too low due to the dropout voltage. v in undervoltage lockout (uvlo) the ltc3613 has two functions that help protect the con- troller in case of input undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. the comparator enables uvlo and locks out the switch- ing action until intv cc rises above 4.2v. once uvlo is released, the comparator does not retrigger uvlo until intv cc falls below 3.65v. this hysteresis prevents oscil- lations when there are disturbances on intv cc . another way to detect an undervoltage condition is to monitor the v in supply. because the run pin has a precision turn-on voltage of 1.2v, one can use a resistor divider from v in to turn on the ic when v in is high enough. the run pin has bias currents that depend on the run voltage as well as sv in voltage. these bias currents should be taken into ac- count when designing the voltage divider and uvlo circuit to prevent faulty conditions. generally for run < 3v a bias current of 1.3a flows out of the run pin, and for run > 3v, correspondingly increasing current flows into the pin, reaching about 35a for run = 6v. soft-start and tracking the ltc3613 has the ability to either soft-start by itself with a capacitor or track the output of an external supply. soft-start or tracking features are achieved not by limiting the maximum output current of the switching regulator but by controlling the regulators output voltage according to the ramp rate on the track/ss pin. when configured to soft-start by itself, a capacitor should be connected to the track/ss pin. track/ss is pulled low until the run pin voltage exceeds 1.2v and uvlo is released, at which point an internal current of 1a charges the soft-start capacitor, c ss , connected to track/ss. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0v to 0.6v on the track/ss pin. the total soft-start time can be calculated as: t softstart =0.6v ? c ss 1a when the ltc3613 is configured to track another supply, a voltage divider can be used from the tracking supply to the track/ss pin to scale the ramp rate appropriately. two common implementations of tracking as shown in figure 6 are coincident and ratiometric. for coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the differential feedback voltage. ratiometric tracking could be achieved by using a different ratio than the differential feedback (figure 7). note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider values to be small enough to make this offset error negligible. intv cc pv in ltc3613 sv in c vcc r vin 3613 f05 v in c in figure 5. setup for v in 5v
ltc3613 21 3613fa applications information time coincident tracking external supply external supply v out voltage v out time 3613 f06 ratiometric tracking voltage figure 6. two different modes of output tracking figure 7. setup for coincident and ratiometric tracking r fb2 ext. v r fb1 coincident tracking setup to track/ss r fb2 v out to v osns + r fb1 to v osns C r1 ext. v r2 r1+ r2 r2 to track/ss r fb2 v out to v osns + r fb1 to v osns C 3613 f07 ratiometric tracking setup 0.6v ext. v phase and frequency synchronization for applications that require better control of emi and switching noise or have special synchronization needs, the ltc3613 can phase and frequency synchronize the turn-on of the switching cycle to an external clock signal applied to the mode/pllin pin. the applied clock signal needs to be within 30% of the rt pin programmed free- running frequency to assure proper frequency and phase lock. the clock signal levels should generally comply to v ih > 2v and v il < 0.5v. the mode/pllin pin has an internal 600k pull-down resistor to ensure pulse-skipping mode if the pin is left floating. the ltc3613 uses the voltages on sv in and v out pins as well as the rt programmed frequency to determine the steady-state on-time as follows: t on v out v in ? f an internal pll system adjusts this on-time dynamically in order to maintain phase and frequency lock with the external clock. the ltc3613 will maintain phase and fre- quency lock under steady-state conditions for v in , v out and load current. as shown in the previous equation, the on-time is a function of the switching regulators output. this output is measured by the v out pin and is used to calculate the required on-time. therefore, simply connecting v out to the regulators local output point is preferable for most applications. however, there could be applications where the internally calculated on-time differs significantly from the real on-time required by the application. for example, if there are differences between the local output point and the remotely regulated output point due to line losses, then the internally calculated on-time will be inaccurate. lower efficiencies in the switching regulator can also cause the real on-time to be significantly different from the internally
ltc3613 22 3613fa applications information calculated on-time (see efficiency considerations). for these circumstances, the voltage on the v out pin can be programmed with a resistive divider from intv cc or from the regulators output itself. note that there is a 500k nominal resistance looking into the v out pin. the pll adjusted on-time achieved after phase locking is the steady-state on-time required by the switching regula- tor, and if the v out programmed on-time is substantially equal to this steady-state on-time, then the pll system does not have to use its 30% frequency lock range for systematic corrections. instead the lock range can be used to correct for component variations or other operating point conditions. if needed, the v out pin can be programmed to achieve the steady-state on-time as required by the applica- tion and therefore maintain constant frequency operation. if the application requires very low on-times approaching minimum on-time, the pll system may not be able to maintain a 30% synchronization range. in fact, there is a possibility of losing phase/frequency lock at minimum on-time, and definitely losing phase/frequency lock for applications requiring less than minimum on-time. this is discussed further under minimum on-time, minimum off-time and dropout operation. loses phase lock due to fast load step establishes frequency lock soon establishes phase lock after ~600s establishes frequency lock soon 3613 f08 phase locked i load clock input sw v out loses phase lock due to fast load release figure 8. phase and frequency locking behavior during transient load conditions during dynamic transient conditions either in the line or load (e.g., load step or release), the ltc3613 may lose phase and frequency lock in the process of achieving faster transient response. for large slew rates (e.g., 10a/ s), phase and frequency lock will be lost (see figure 8) until the system returns back to a steady-state condition at which point the device will resume frequency lock and eventually achieve phase lock to the external clock. for relatively small slew rates (10a/s), phase and frequency lock can still be maintained. for light loading conditions, the phase and frequency synchronization will be active if there is a clock input ap- plied. if there is no clock input during light loading, then the switching frequency is based on what the mode/pllin pin is tied to. when mode/pllin is tied to intv cc , the ltc3613 will operate in forced continuous mode at the rt programmed free-running frequency. when mode/pllin pin is tied to signal ground, the ltc3613 will operate in pulse-skipping discontinuous conduction mode for light loading and will switch to continuous conduction (at the free-running frequency) for normal and heavy loads.
ltc3613 23 3613fa applications information minimum on-time, minimum off-time and dropout operation the minimum on-time is the smallest duration of time in which the ltc3613 can keep its top power mosfet in its on state. this minimum on-time is 65ns for the ltc3613 and is achieved when the v out pin is tied to its minimum value of 0.6v while the pv in is tied to its maximum value of 24v. for larger values of v out or smaller values of pv in , the minimum on-time achievable will be longer than 65ns. the minimum on-time will have a dependency on the operating conditions of the switching regulator, but is intended to be smaller for high step-down ratio applica- tions that will require low on-times. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: d min = f ? t on(min) where t on(min) is the minimum on-time for the switching regulator. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. if the application requires a smaller than minimum duty cycle, the output voltage will still remain in regulation, but the switching frequency will decrease from its programmed value or lose frequency synchronization if using an external clock. depending on the application, this may not be of critical importance. the minimum off-time is the smallest duration of time that the top power mosfet can be turned off and then immediately turned back on. the minimum off-time that the ltc3613 can achieve is 105ns. the minimum off-time limit imposes a maximum duty cycle of: d max = 1 C f ? t off(min) where t off(min) is the minimum off-time of the switching regulator. reducing the operating frequency alleviates the maximum duty cycle constraint. if the maximum duty cycle is reached, due to a drooping input voltage for example, then the output will drop out of regulation. the minimum input voltage to avoid dropout is: v in(min) = v out d max at the onset of dropout, there is a region of pv in about 500mv that generates two discrete off-times, one being the minimum off-time and the other being an off-time that is about 40ns to 60ns larger than the minimum off-time. this secondary off-time is due to the longer delay in trip- ping the internal current comparator. the two off-times average out to the required duty cycle to keep the output in regulation with the output ripple remaining the same. however, there is higher sw node jitter, especially appar- ent when synchronized to an external clock. depending on the application, this may not be of critical importance. fault conditions: current limiting and overvoltage the maximum inductor current is inherently limited in a current mode controller by the maximum sense voltage. in the ltc3613, the maximum sense voltage is controlled by the voltage on the v rng pin. with valley current mode control, the maximum sense voltage and the sense re- sistance determine the maximum allowed inductor valley current. the corresponding output current limit is: i limit = v sense(max) r sense + 1 2 ? i l the current limit value should be checked to ensure that i limit(min) > i out(max) . the current limit value should be greater than the inductor current required to produce maximum output power at the worst-case efficiency. worst-case efficiency typically occurs at the highest pv in and highest ambient temperature.
ltc3613 24 3613fa applications information to further limit current in the event of a short circuit to ground, the ltc3613 includes foldback current limiting. if the output fails by more than 50%, then the maximum sense voltage is progressively lowered to about one-fourth of its full value. if the output exceeds 7.5% of the programmed value, then it is considered as an overvoltage (ov) condition. in such a case, the top mosfet is immediately turned off and the bottom mosfet is turned on indefinitely until the ov condition is removed. current limiting is not ac- tive during an ov. if the output returns to a nominal level, then normal operation resumes. if the ov persists a long time, the current through the inductor could exceed its maximum rating. opti-loop compensation opti-loop compensation, through the availability of the ith pin, allows the transient response to be optimized for a wide range of loads and output capacitors. the ith pin not only allows optimization of the control loop behavior but also provides a test point for the step-down regulator s dc-coupled and ac-filtered closed-loop response. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at this pin. the ith series r ith -c ith1 filter sets the dominant pole-zero loop compensation. additionally, a small capacitor placed from the ith pin to sgnd, c ith2 , may be required to at- tenuate high frequency noise. the values can be modified to optimize transient response once the final pcb layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. the general goal of opti-loop compensation is to realize a fast but stable ith response with minimal output droop due to the load step. for a detailed explanation of opti-loop compensation, refer to application note 76. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im- mediately shifts by an amount equal to i load ? esr, where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. connecting a resistive load in series with a power mosfet, then placing the two directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load-step condi- tion. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated feedback loop response. the gain of the loop increases with r ith and the bandwidth of the loop increases with decreasing c ith1 . if r ith is increased by the same factor that c ith1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, a feedforward capacitor, c ff , can be added to improve the high frequency response, as shown in figure 1. capacitor c ff provides phase lead by creating a high frequency zero with r fb2 which improves the phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate overall performance of the step-down regulator.
ltc3613 25 3613fa applications information in some applications, a more severe transient can be caused by switching in loads with large (>10f) input capacitors. if the switch connecting the load has low resistance and is driven quickly, then the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifically for this purpose and usually incorporates cur- rent limiting, short-circuit protection and soft starting. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: %efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses: 1. i 2 r losses. these arise from the resistances of the mosfets, inductor and pc board traces and cause the efficiency to drop at high output currents. in continuous mode the average output current flows though the inductor l, but is chopped between the top and bottom mosfets. 2. transition loss. this loss arises from the brief amount of time the top mosfet spends in the saturated region during switch node transitions. it depends upon the input voltage, load current, driver strength and mosfet capacitance, among other factors. the loss is significant at input voltages above 20v. 3. intv cc current. this is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge, dq, moves from intv cc to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the controller i q current. supplying intv cc power through extv cc could save several points of efficiency, especially for high v in ap- plications. connecting extv cc to an output-derived source will scale the v in current required for the driver and controller circuits by a factor of duty cycle/effi- ciency. for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 4. c in loss. the input capacitor has the difficult job of filtering the large rms input current to the regulator. it must have a very low esr to minimize the ac i 2 r loss and sufficient capacitance to prevent the rms current from causing additional upstream losses in cabling, fuses or batteries. other losses, which include the c out esr loss, bottom mosfet reverse-recovery loss and inductor core loss generally account for less than 2% additional loss. when making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. if you make a change and the input current decreases, then the efficiency has increased. if there is no change in input current there is no change in efficiency. power losses in the switching regulator will reflect as a longer than ideal on-time. this efficiency accounted on- time in continuous mode can be calculated as: t on(real) t on(ideal) efficiency
ltc3613 26 3613fa applications information design example consider a step-down converter with v in = 6v to 24v, v out = 1.2v, i out(max) = 15a, and f = 350khz (see figure 9). the regulated output voltage is determined by: v out =0.6v ? 1+ r fb2 r fb1 ? ? ? ? ? ? using a 20k resistor from v osns + to v osns C , the top feedback resistor is also 20k. the frequency is programmed by: r t k [] = 41550 fkhz [] C2.2= 41550 350 C2.2 116.5k select the nearest standard value of 115k. the minimum on-time occurs for maximum v in and should be greater than 65ns, which is the best that the ltc3613 can achieve. the minimum on-time for this application is: t on(min) = v out v in(max) ? f = 1.2v 24v ? 350khz 143ns set the inductor value to give 40% ripple current at maxi- mum v in : l= 1.2v 350khz ? 40% ? 15a ? 1C 1.2v 24v ? ? ? ? ? ? 0.54h select 0.56h, which is the nearest standard value. pv in sv in v out pgood run v rng sense C sense + r pgd 100k intv cc r ith 28k r t 115k r dcr 3.09k ltc3613 r fb2 20k r fb1 20k c out1 330f 2.5v 2 c out2 100f 2 l1 0.56h sw d b c ss 0.1f r div1 52.3k r div2 10k c ith1 220pf c ith2 100pf 3613 f10 v in 6v to 24v v out 1.2v 15a c dcr 0.1f c b 0.1f c vcc 4.7f c in1 : sanyo 25svpd82m c out1 : sanyo 2r5tpe330m9 d b : central cmdsh-3 l1: vishay ihlp4040dz-056h track/ss ith rt mode/pllin extv cc sgnd boost intv cc intv cc pgnd v osns + v osns C c in2 10f c in1 82f 25v + + 350khz load current (a) 0.1 40 efficiency (%) 60 70 80 100 1 10 100 3613 f10a 20 30 50 90 10 0 v in = 12v v out = 1.2v pulse-skipping mode forced continuous mode figure 9. 1.2v, 15a, 350khz step-down converter
ltc3613 27 3613fa applications information the resulting maximum ripple current is: i l = 1.2v 350khz ? 0.56h ? 1C 1.2v 24v ? ? ? ? ? ? 5.8a often in high power applications, dcr current sensing is preferred over r sense in order to maximize efficiency. in order to determine the dcr filter values, first the induc- tor manufacturer has to be chosen. for this design, the vishay ihlp-4040dz-01 model is chosen with a value of 0.56h and dcr max =1.8m. this implies that: v sense(max) = dcr max at 25c ? [1 + 0.4% (t l(max) C 25c)] ? [i out(max) C i l /2] = 1.8m ? [1 + 0.4% (100c C 25c)] ? [15a C 5.8a/2] 28.3mv the maximum sense voltage is within the range that ltc3613 can handle without any additional scaling. there- fore, the dcr filter consists of a simple rc filter across the inductor. if the c is chosen to be 0.1f, then the r can be calculated as: r dcr = l dcr max ? c dcr = 0.56h 1.8m ? 0.1f 3.11k the closest standard value is 3.09k. the resulting value of v rng with a 50% design margin factor is: v rng = v sense(max) /0.05 ? mf = 28.3mv/0.05 ? 1.5 850mv to generate the v rng voltage, connect a resistive divider from intv cc to sgnd with r div1 = 52.3k and r div2 = 10k. select c in to give an rms current rating greater than 7a at 75c. the output capacitor c out is chosen for a low esr of 4.5m to minimize output voltage changes due to inductor ripple current and load steps. the output voltage ripple is given as: v out(ripple) = i l(max) ? esr = (5.8a)(4.5m) 26mv however, a 0a to 10a load step will cause an output change of up to: v out(step) = i load ? esr = (10a)(4.5m) = 45mv optional 100f ceramic output capacitors are included to minimize the effect of esr and esl in the output ripple and to improve load step response. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3613. ? multilayer boards with dedicated ground layers are preferable for reduced noise and for heat sinking pur- poses. use wide rails and/or entire planes for v in , v out and pgnd nodes for good filtering and minimal copper loss. flood unused areas of all layers with copper for better heat sinking. ? keep signal and power grounds separate except at the point where they are shorted together. short signal and power ground together only at a single point with a nar- row pcb trace (or single via in a multilayer board). all power train components should be referenced to power ground and all small-signal components (e.g., c ith1 , r t , c ss etc.) should be referenced to signal ground. ? place c in , inductor, sense resistor (if used), and primary c out capacitors close together in one compact area. the sw node should be compact but be large enough to handle the inductor currents without large copper losses. connect pv in as close as possible to the (+) plate of c in capacitor(s) that provides the bulk of the ac current (these are normally the ceramic capaci- tors), and connect pgnd as close as possible to the (C) terminal of the same c in capacitor(s). the high di/ dt loop formed by c in , the top mosfet, and the bot- tom mosfet should have short leads and pcb trace lengths to minimize high frequency emi and voltage stress from inductive ringing. the (C) terminal of the primary c out capacitor(s) which filter the bulk of the inductor ripple current (these are normally the ceramic capacitors) should also be connected close to the (C) terminal of c in .
ltc3613 28 3613fa applications information ? place the boost, pv in , sw, and pgnd pins facing the power train components. keep high dv/dt signals on boost and sw away from sensitive small-signal traces and components. ? for r sense current sensing, place the sense resistor close to the inductor on the output side. use a kelvin (4-wire) connection across the sense resistor and route the traces together as a differential pair. rc filter the differential sense signal close to sense + /sense C pins, placing the filter capacitor as close as possible to the pins. for dcr sensing, kelvin connect across the inductor and place the dcr sensing resistor closer to the sw node and further away from the sense + / sense C pins. place the dcr capacitor close to the sense + /sense C pins. ? place the resistive feedback divider r fb1/2 as close as possible to v osns + /v osns C pins and route the remote output and ground traces together as a differential pair and terminate as close to the regulation point as possible (preferably kelvin connect across the capacitor at the remote output point). ? place the ceramic c vcc capacitor as close as possible to the intv cc and pgnd pins. likewise, the c b capacitor should be as close as possible to boost and sw pins. these capacitors provide the gate charging currents for the onboard power mosfets. ? place small-signal components as close to their respec- tive pins as possible. this minimizes the possibility of pcb noise coupling into these pins. give priority to v osns + /v osns C , sense + /sense C , ith, rt and v rng pins. use sufficient isolation when routing a clock signal into mode/pllin pin so that the clock does not couple into sensitive small-signal pins. ? filter the sv in input to the ltc3613 with a simple rc filter close to the pin. the rc filter should be referenced to signal ground.
ltc3613 29 3613fa applications information v rng sv in pv in mode/pllin v out pgood run sense C sense + r pgd 100k r f1 10 r f2 10 intv cc r vin 2.2 ltc3613 r fb2 15k r fb1 10k c in1 : sanyo 25svpd82m c out1 : sanyo 2r5tpe330m9 d b : central cmdsh-3 l1: coiltronics fp1109-r47 d b intv cc c out1 330f 2.5v 2 c out2 100f 2 l1 0.47h r sense 1.5m c b 0.1f c in2 22f 2 c in1 82f 25v v out 1.5v 15a 3833 f11 v in 4.5v to 24v c vin 0.1f c f 1000pf c vcc 4.7f track/ss ith rt r t 115k c ith1 270pf c ith2 47pf c ss 0.1f r ith 21k extv cc sgnd boost sw intv cc pgnd v osns + v osns C + + efficiency figure 10. 1.5v, 15a, 350khz high current step-down converter load current (a) 0.1 40 efficiency (%) 80 90 100 1 10 100 3613 f11a 70 60 50 pulse-skipping mode forced continuous mode v in = 12v v out = 1.5v
ltc3613 30 3613fa efficiency sv in pv in v out pgood run v rng sense C sense + r pgd 100k intv cc r ith 49.9k 30.9k 10k r t 205k r vin 2.2 r dcr 8.25k r b 10 ltc3613 c out1 330f 6.3v 2 c in1 : nichicon ucj1h101mcl1gs c out1 : sanyo 6tpe330mil d b : diodes inc. sdm10k45 l1: coilcraft xal1010-472me c out2 100f 2 r fb2 147k r fb1 20k l1 4.7h d b c ss 0.1f c ith1 1000pf c vin 0.1f 3613 ta02 v in 7v to 24v v out 5v 8a c dcr 0.1f c b 0.1f c vcc 4.7f track/ss ith rt mode/pllin extv cc sgnd boost sw intv cc intv cc pgnd v osns + v osns C c in2 10f 3 c in1 100f 50v + + load current (a) 0.01 0.1 70 efficiency (%) 90 95 100 11 0 3613 ta03 85 80 75 forced continuous mode pulse-skipping mode v in = 12v v out = 5v v in = 12v v out = 5v typical applications figure 11. 5v, 8a, 200khz high efficiency step-down converter
ltc3613 31 3613fa typical applications figure 12. 0.6v, 10a, 200khz low output voltage step-down converter sv in pv in v out pgood mode/pllin v rng run sense C sense + r pgd 100k intv cc r ith 17.4k r t 205k c ss 0.1f c ith1 470pf ltc3613 c out2 100f 2 c out1 330f 2.5v 2 l1 1h r sense 3m c b 0.1f c in2 10f 3 v out 0.6v 10a 3613 ta04 v in 4.5v to 14v c f 1000pf c vcc 4.7f d b track/ss ith rt extv cc sgnd boost sw intv cc intv cc pgnd v osns + v osns C r vin 2.2 r f2 10 r f1 10 c vin 0.1f c in1 : sanyo 25svpd82m c out : sanyo 2r5tpe330m9 d b : diodes inc. sdm10k45 l1: ihlp-2525ezerr82m01 + c in1 82f 25v + load current (a) 0 10 50 40 20 30 100 80 90 70 60 3613 ta05 efficiency (%) 0.01 10 0.10 1 v in = 12v v out = 0.6v forced continuous mode pulse-skipping mode efficiency
ltc3613 32 3613fa typical applications v in v out pgood run v rng sense C sense + r pgd 100k intv cc r ith 10k r t 115k ltc3613 r fb2 20k r fb1 20k c out1 330f 2.5v 4 c out2 100f 2 v out 1.2v 30a 0.47h 0.47h 2m 2m sw d b c ss 0.1f r div1 56.2k r div2 10k c ith1 330pf c ith2 47pf 3613 ta12 v in 6v to 24v c dcr 0.1f c b 0.1f c vcc 4.7f track/ss ith rt mode/pllin extv cc sgnd boost intv cc intv cc pgnd v osns + v osns C c in2 10f c in1 82f 25v + + 350khz v in v out pgood run v rng sense C sense + r t 115k ltc3613 c out2 100f 2 sw d b 47pf ( 1 2 = 180 out of phase) c dcr 0.1f c b 0.1f c vcc 4.7f c in1 : sanyo 25svpd82m c out1 : sanyo 2r5tpe330m9 d b : central cmdsh-3 l1: coiltronics fp1109-r47 track/ss ith rt mode/pllin extv cc sgnd boost intv cc intv cc pgnd v osns + v osns C c in2 10f c in1 82f 25v + 350khz figure 13. 2 phase, 1.2v, 30a, 350khz step-down converter
ltc3613 33 3613fa typical applications load current (a) 0.1 efficiency (%) 80 90 60 70 10 3613 ta013 40 50 20 30 0 10 1 100 100 v in = 12v v out = 1.2v forced continuous mode 20s/div 3613 ta14 v out(ac) 100mv/div i load 10a/div load step = 0a to 30a v in = 12v efficiency transient response
ltc3613 34 3613fa package description 7.00 bsc 9.00 bsc 1719 28 bottom view (bottom metallization details) top view 0.50 bsc 0.90 0.10 // ccc c 0.00 C 0.05 mlp56 qfn rev ? 0310 nx b seating plane 5 6 4 0.08 c aaa c aaa c m a cb bbb nx a b 2x 2x 45 1 12 29 44 note: 1. dimensioning and tolerancing conform to asme y14.5m-1994 2. all dimensions are in millimeters, angles are in degrees ( ) 3 the location of the terminal #1 identifier and terminal numbering convention conforms to jedec publication 95 spp-002 4 dimension b applies to metallized terminal and is measured between 0.20mm and 0.30mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension b should not be measured in that radius area. 5 coplanarity applies to the terminals and all other surface metallization 6 drawing shown are for illustration only symbol aaa bbb ccc tolerance 0.15 0.10 0.10 pad 1 corner recommended solder pad layout top view 0.50 bsc 2.90 ref 2.63 ref 1.97 0.10 1.97 0.05 3.15 0.10 3.15 0.05 pin 1 id 7.50 0.05 9.50 0.05 package outline 0.40 0.05 4.06 0.10 3.82 ref 4.06 0.05 3.82 ref pin 1 4.76 0.10 1.50 ref 1.78 ref 4.27 0.10 4.27 0.05 1.35 0.05 2.25 0.10 0.25 0.05 1.78 ref 1.35 0.05 0.25 0.05 0.40 0.05 16 56 2.63 ref 2.90 ref 4.76 0.05 3.82 ref 0.58 0.05 0.95 ref 3 wkh package 56-lead qfn multipad (7mm 9mm) (reference ltc dwg # 05-08-1870 rev ?) 2.25 0.05 1.50 ref peae refer ://.near.cm/en/acan/ fr e m recen acae ran.
ltc3613 35 3613fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/12 clarified electrical characteristics clarified pin functions modified application circuit 3, 4 8 33
ltc3613 36 3613fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0712 rev a ? printed in usa related parts typical application r div1 0 sv in pv in v out extv cc v rng run sense C sense + r pgd 100k intv cc r ith 20k r t 40.2k c ss 0.1f c ith1 220pf ltc3613 r fb2 147k c ff 22pf r fb1 20k c out1 22f 2 l1 1.2h r sense 10m c b 0.1f c in1 47f 35v 3613 ta10 v in 7v to 24v v out 5v 4a c in2 4.7f 2 c vcc 4.7f d b track/ss ith rt mode/pllin pgood sgnd boost sw intv cc intv cc pgnd v osns + v osns C r vin 2.2 r f1 10 r f2 10 c vin 0.1f c f 1000pf c in1 : kemet t521x476m035ate070 d b : diodes, inc. sdm10k45 l1: wrth 744313120 + high frequency 5v, 4a, 1mhz step-down converter load current (a) 0 50 30 40 10 20 90 100 80 70 60 3613 ta11 efficiency (%) 0.01 10 0.10 1 forced continuous mode pulse- skipping mode v in = 12v v out = 5v efficiency part number description comments ltc3602 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4.5v to 10v, v out(min) = 0.6v, i q = 75a, i sd <1a, 4mm 4mm qfn-20, tssop-16e packages ltc3608 18v, 8a (i out ), 1mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 18v, v out(min) = 0.6v, i q = 900a, i sd <15a, 7mm 8mm qfn-52 package LTC3610 24v, 12a (i out ), 1mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 24v, v out(min) = 0.6v, i q = 900a, i sd <15a, 9mm 9mm qfn-64 package ltc3611 32v, 10a (i out ), 1mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 4v to 32v, v out(min) = 0.6v, i q = 900a, i sd <15a, 9mm 9mm qfn-64 package ltc3414/ ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd <1a, tssop20e package ltc3415 7a (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 450a, i sd <1a, 5mm 7mm qfn-38 package ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% efficiency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 380a, i sd <1a, 5mm 7mm qfn-38 package ltm4600hv 10a complete switch mode power supply 92% ef?ciency, v in : 4.5v to 28v, v out : 0.6v, true current mode control, ultrafast transient response ltm4601hv 12a complete switch mode power supply 92% ef?ciency, v in : 4.5v to 28v, v out : 0.6v, true current mode control, ultrafast transient response ltm4602hv 6a complete switch mode power supply 92% efficiency, v in : 4.5v to 28v, v out : 0.6v, true current mode control, ultrafast transient response ltm4603hv 6a complete switch mode power supply 93% efficiency, v in : 4.5v to 28v, with pll, output tracking and margining

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